1. Field of the Invention
This disclosure relates to graphics systems and, more particularly, to embedded frame buffers integrated into the graphic systems.
2. Description of the Related Art
The basic components of a video subsystem include a graphics controller, frame buffer, palette/DAC and software device drivers. A VRAM based graphics subsystem for personal computers is typically arranged with a graphics controller device connected to a peripheral component bus, and random access port of one or more VRAM devices.
The center of the graphics subsystem includes a graphics controller (also called a rendering engine), whose basic function is to rasterize the graphical data, defined as conversion of high level geometric primitives issued by software device drivers on a main central processing unit (CPU) to low level pixel values. Each low level pixel value is represented as a binary number composed of either a single 4 bit, 8 bit, 16 bit, 24 bit or 32 bit number, depending on mode selection. The graphics controller also includes a memory controller which is used to control access to a dedicated memory space, which includes a frame buffer and graphics processor memory. The memory controller generates the VRAM refresh signals, and controls the screen refresh process.
An image of the entire screen is stored in the frame buffer. Each pixel value is associated with an x and y pixel location on the screen (with an origin in the upper left corner of the screen). The graphics controller implements an address translation, which maps these x, y pixel locations in screen coordinates to a linear byte address. This linear address is used by a memory controller built into the graphics controller to generate memory control signals and row and column addresses.
The pixel data generated by the graphics controller is transferred to the VRAM frame buffer according to generated row and column addresses, where it is stored and used as the source for refreshing the display at a constant rate. During a screen refresh operation, the graphics controller initiates a transfer of data between the DRAM portion and the SAM memory inside the VRAM, and provides a clock for scanning out the pixel data from the serial access port of the VRAM. The serial port of the VRAM is connected to a Palette/DAC where the pixel data is expanded to 24 bits and is converted to an analog signal to drive a cathode ray tube (CRT), or is directly used to drive a liquid crystal display (LCD).
Video random access memory (VRAM) includes a dynamic random access memory (DRAM) which is interfaced to a serial register/serial access memory (SAM). VRAM typically supports three basic operations which include: bidirectional random access to the DRAM, bidirectional serial access to the SAM and bidirectional data transfer between any DRAM row and the SAM.
The SAM memory is typically the size of a single row (or 1/2 row) of DRAM memory. This arrangement allows a single transfer of an entire row of DRAM memory to the SAM in a single DRAM access cycle, thereby allowing the data in the SAM to be clocked out of a serial port at a high rate, independent of the DRAM random access port. In a graphics subsystem, VRAM stores an electrical image of the display and is known as a frame buffer.
The Palette/DAC, also known as RAMDAC or palette, provides the function of serializing the data from the VRAM memory into a single pixel bit stream, and passing the pixels to a palette (look-up table) followed by a digital-to-analog converter (DAC) to drive a CRT device.
The palette provides lossless image decompression when the screen image contains fewer than 256 unique colors, as defined by the VGA standard. Prior to the screen refresh, the palette is loaded with 256 mixtures of 8 bit red, green and blue components by the graphics controller. An 8 bit color stored in the frame buffer is applied to the palette to select one of these 256 colors from over 16 million possibilities. The 8 bit color components are then applied to a DAC where they are converted to RGB analog signals for driving a CRT display. The digital color components can also be applied to off-chip driving circuits for driving an LCD display simultaneously. The Palette/DAC part usually also provides a palette bypass path to allow direct storage of the "true" 24 bit color mixtures for direct control of the screen colors. The palette provides a method to store only those colors in the frame buffer that are used to create the screen image, thereby reducing memory requirements. This is at the expense of limiting the maximum number of unique colors that are displayable on the screen at any given time to 256.
In conventional graphics subsystems, VRAM memory devices use separate memory banks thereby expending more energy than necessary. Therefore, a need exists for integrating VRAM devices and a Palette/DAC in a single device. Such an integration would provide a lower power for operation by minimizing the transfer of data between discrete devices. A need also exists for expanding graphics systems by using multiple devices and operating one device as a master device and the others as slave devices thereby permitting a single device to generate synchronizing signals and convert digital data to an analog signal to drive a CRT display.